# IEEE Journal of Solid-State Circuits

**Type:** Journals  
**Canonical URL:** https://scholariq.org/journals/ieee-journal-of-solid-state-circuits/

## Facts

| Field | Value |
| --- | --- |
| Open Access | false |
| ISSN-L | 0018-9200 |
| ISSNs | 0018-9200,1558-173X |
| OpenAlex ID | https://openalex.org/S83637746 |
| Publisher | Institute of Electrical and Electronics Engineers |

## Journal papers

Showing 12 of 13.

- [A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-$\mu{\hbox {m}}$ Technology](https://scholariq.org/papers/a-passive-uhf-rf-identification-cmos-tag-ic-using-ferroelectric-ram-in-0-35-mu/)
- [A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput](https://scholariq.org/papers/a-90-nm-1-8-v-512-mb-diode-switch-pram-with-266-mb-s-read-throughput/)
- [Transient Analysis of MOS Transistors](https://scholariq.org/papers/transient-analysis-of-mos-transistors-2/)
- [A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation](https://scholariq.org/papers/a-0-1-mu-hbox-m-1-8-v-256-mb-phase-change-random-access-memory-pram-with-66-mhz/)
- [A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS](https://scholariq.org/papers/a-28-gb-s-560-mw-multi-standard-serdes-with-single-stage-analog-front-end-and-14/)
- [A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter](https://scholariq.org/papers/a-2-1-to-2-8-ghz-low-phase-noise-all-digital-frequency-synthesizer-with-a-time/)
- [A 30-MHz–2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems](https://scholariq.org/papers/a-30-mhz-2-4-ghz-cmos-receiver-with-integrated-rf-filter-and-dynamic-range/)
- [A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS](https://scholariq.org/papers/a-1-0625-sim-14-025-gb-s-multi-media-transceiver-with-full-rate-source-series/)
- [A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio](https://scholariq.org/papers/a-widely-tunable-reconfigurable-cmos-analog-baseband-ic-for-software-defined/)
- [A 1.8–GΩ Input-Impedance 0.15–μV Input-Referred–Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction](https://scholariq.org/papers/a-1-8-g-input-impedance-0-15-v-input-referred-ripple-chopper-amplifier-with/)
- [A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-<tex>$muhbox m$</tex>SiGe BiCMOS Technology](https://scholariq.org/papers/a-1-tap-40-gb-s-look-ahead-decision-feedback-equalizer-in-0-18-and-lt-tex-and-gt/)
- [A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme](https://scholariq.org/papers/a-low-if-zero-if-reconfigurable-analog-baseband-ic-with-an-i-q-imbalance/)

---
Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.