# An Optimized 90nm CMOS PLL with Reduced Power Consumption and Locking Time

**Type:** Papers  
**Canonical URL:** https://scholariq.org/papers/an-optimized-90nm-cmos-pll-with-reduced-power-consumption-and-locking-time/

## Facts

| Field | Value |
| --- | --- |
| Author Names | Aditya Nagar,Satyam Barot,Amit Kumar |
| Citations | 0 |
| DOI | 10.1109/iconat66879.2025.11362871 |
| Fields | Engineering |
| Open Access | false |
| OA Status | closed |
| OpenAlex ID | https://openalex.org/W7126244765 |
| Type | conference-paper |
| Year | 2025 |

## Paper authors

- [Aditya Nagar](https://scholariq.org/researchers/aditya-nagar/)

## Paper primary topic

- [Advancements in PLL and VCO Technologies](https://scholariq.org/topics/advancements-in-pll-and-vco-technologies/)

## Paper topics

- [Advancements in PLL and VCO Technologies](https://scholariq.org/topics/advancements-in-pll-and-vco-technologies/)
- [Low-power high-performance VLSI design](https://scholariq.org/topics/low-power-high-performance-vlsi-design/)
- [Electromagnetic Compatibility and Noise Suppression](https://scholariq.org/topics/electromagnetic-compatibility-and-noise-suppression/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.