# Delay-insensitive gate-level pipelining

**Type:** Papers  
**Canonical URL:** https://scholariq.org/papers/delay-insensitive-gate-level-pipelining/

## Facts

| Field | Value |
| --- | --- |
| Author Names | Scott C. Smith,Ronald F. DeMara,J.S. Yuan,M. Hagedorn,D. Ferguson |
| Citations | 70 |
| DOI | 10.1016/s0167-9260(01)00013-x |
| Fields | Computer Science,Engineering |
| Open Access | true |
| OA Status | green |
| OA URL | https://stars.library.ucf.edu/facultybib2000/2955 |
| OpenAlex ID | https://openalex.org/W1993922697 |
| Type | article |
| Year | 2001 |

## Paper authors

- [Scott C. Smith](https://scholariq.org/researchers/scott-c-smith/)

## Paper primary topic

- [Low-power high-performance VLSI design](https://scholariq.org/topics/low-power-high-performance-vlsi-design/)

## Paper topics

- [Low-power high-performance VLSI design](https://scholariq.org/topics/low-power-high-performance-vlsi-design/)
- [VLSI and FPGA Design Techniques](https://scholariq.org/topics/vlsi-and-fpga-design-techniques/)
- [Interconnection Networks and Systems](https://scholariq.org/topics/interconnection-networks-and-systems/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.