# Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

**Type:** Papers  
**Canonical URL:** https://scholariq.org/papers/timing-yield-driven-clock-skew-scheduling-considering-non-gaussian-distributions/

## Facts

| Field | Value |
| --- | --- |
| Author Names | Yi Wang,Wai-Shing Luk,Xuan Zeng,Jun Tao,Changhao Yan,Jiarong Tong,Wei Cai,Jia Ni |
| Citations | 14 |
| DOI | 10.1145/1391469.1391525 |
| Fields | Computer Science,Engineering |
| Open Access | false |
| OA Status | closed |
| OpenAlex ID | https://openalex.org/W2168129320 |
| Type | conference-paper |
| Year | 2008 |

## Paper authors

- [Jiarong Tong](https://scholariq.org/researchers/jiarong-tong/)

## Paper primary topic

- [Low-power high-performance VLSI design](https://scholariq.org/topics/low-power-high-performance-vlsi-design/)

## Paper topics

- [Low-power high-performance VLSI design](https://scholariq.org/topics/low-power-high-performance-vlsi-design/)
- [VLSI and FPGA Design Techniques](https://scholariq.org/topics/vlsi-and-fpga-design-techniques/)
- [VLSI and Analog Circuit Testing](https://scholariq.org/topics/vlsi-and-analog-circuit-testing/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.