# Digital Filter Design and Implementation

**Type:** Topics  
**Canonical URL:** https://scholariq.org/topics/digital-filter-design-and-implementation/

## Facts

| Field | Value |
| --- | --- |
| Description | This cluster of papers covers advanced techniques in digital signal processing, including FFT algorithms, filter banks, DCT approximation, FIR filter design, multiplierless algorithms, digital audio coding, software radio applications, polyphase filters, variable fractional delay filters, and the use of semidefinite programming for optimization. |
| Domain | Physical Sciences |
| Field | Computer Science |
| OpenAlex ID | t11034 |
| Works | 13 |

## Topic papers all

- [CORDIC-based VLSI architectures for digital signal processing](https://scholariq.org/papers/cordic-based-vlsi-architectures-for-digital-signal-processing/)
- [Compression of hyperspectral imagery](https://scholariq.org/papers/compression-of-hyperspectral-imagery/)
- [Computation of Fractional Order Derivative and Integral via Power Series Expansion and Signal Modelling](https://scholariq.org/papers/computation-of-fractional-order-derivative-and-integral-via-power-series/)
- [A low-power 64-point pipeline FFT/IFFT processor for OFDM applications](https://scholariq.org/papers/a-low-power-64-point-pipeline-fft-ifft-processor-for-ofdm-applications/)
- [An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications](https://scholariq.org/papers/an-indexed-scaling-pipelined-fft-processor-for-ofdm-based-wpan-applications/)
- [Discrete Signal Processing](https://scholariq.org/papers/discrete-signal-processing/)
- [ECG compression using the context modeling arithmetic coding with dynamic learning vector–scalar quantization](https://scholariq.org/papers/ecg-compression-using-the-context-modeling-arithmetic-coding-with-dynamic/)
- [Non-uniform Haar wavelets](https://scholariq.org/papers/non-uniform-haar-wavelets/)
- [A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications](https://scholariq.org/papers/a-novel-low-power-64-point-pipelined-fft-ifft-processor-for-ofdm-applications/)
- [Improved Digital Rational Approximation of the Operator $$S^{\alpha }$$ S α Using Second-Order s-to-z Transform and Signal Modeling](https://scholariq.org/papers/improved-digital-rational-approximation-of-the-operator-s-alpha-s-using-second/)
- [Performance analysis of new adaptive decision based median filter on FPGA for impulsive noise filtering](https://scholariq.org/papers/performance-analysis-of-new-adaptive-decision-based-median-filter-on-fpga-for/)
- [Low power VLSI transposed structure FIR filter using shift/add architecture](https://scholariq.org/papers/low-power-vlsi-transposed-structure-fir-filter-using-shift-add-architecture/)
- [Performance analysis and implementation method of VMF and EVMF for removing of impulse noise on FPGA](https://scholariq.org/papers/performance-analysis-and-implementation-method-of-vmf-and-evmf-for-removing-of/)

## Topic primary papers

- [A low-power 64-point pipeline FFT/IFFT processor for OFDM applications](https://scholariq.org/papers/a-low-power-64-point-pipeline-fft-ifft-processor-for-ofdm-applications/)
- [An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications](https://scholariq.org/papers/an-indexed-scaling-pipelined-fft-processor-for-ofdm-based-wpan-applications/)
- [Discrete Signal Processing](https://scholariq.org/papers/discrete-signal-processing/)
- [A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications](https://scholariq.org/papers/a-novel-low-power-64-point-pipelined-fft-ifft-processor-for-ofdm-applications/)
- [Low power VLSI transposed structure FIR filter using shift/add architecture](https://scholariq.org/papers/low-power-vlsi-transposed-structure-fir-filter-using-shift-add-architecture/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.