# Interconnection Networks and Systems

**Type:** Topics  
**Canonical URL:** https://scholariq.org/topics/interconnection-networks-and-systems/

## Facts

| Field | Value |
| --- | --- |
| Description | This cluster of papers focuses on the design, architecture, and optimization of Networks on Chip (NoC) within System-on-Chip (SoC) designs. It covers topics such as interconnection networks, routing algorithms, performance evaluation, power optimization, wireless interconnects, fault tolerance, and multi-core processors. |
| Domain | Physical Sciences |
| Field | Computer Science |
| OpenAlex ID | t10829 |
| Works | 19 |

## Topic papers all

Showing 15 of 19.

- [Accelerating Compute-Intensive Applications with GPUs and FPGAs](https://scholariq.org/papers/accelerating-compute-intensive-applications-with-gpus-and-fpgas/)
- [Microarchitecture of a High-Radix Router](https://scholariq.org/papers/microarchitecture-of-a-high-radix-router/)
- [Towards Energy-Efficient Routing in Satellite Networks](https://scholariq.org/papers/towards-energy-efficient-routing-in-satellite-networks/)
- [Designing Asynchronous Circuits using NULL Convention Logic (NCL)](https://scholariq.org/papers/designing-asynchronous-circuits-using-null-convention-logic-ncl/)
- [NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?](https://scholariq.org/papers/noc-architectures-for-silicon-interposer-systems-why-pay-for-more-wires-when-you/)
- [Looking back on the language and hardware revolutions](https://scholariq.org/papers/looking-back-on-the-language-and-hardware-revolutions/)
- [Delay-insensitive gate-level pipelining](https://scholariq.org/papers/delay-insensitive-gate-level-pipelining/)
- [1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS](https://scholariq.org/papers/1-1-v-1-ghz-communications-router-with-on-chip-body-bias-in-150-nm-cmos/)
- [Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems](https://scholariq.org/papers/hardware-resource-virtualization-for-dynamically-partially-reconfigurable/)
- [Efficient Adaptive Scheduling of Multiprocessors with Stable Parallelism Feedback](https://scholariq.org/papers/efficient-adaptive-scheduling-of-multiprocessors-with-stable-parallelism/)
- [Xmesh: A Mesh-Like Topology for Network on Chip](https://scholariq.org/papers/xmesh-a-mesh-like-topology-for-network-on-chip/)
- [On Efficient Service Function Chaining in Hybrid Software Defined Networks](https://scholariq.org/papers/on-efficient-service-function-chaining-in-hybrid-software-defined-networks/)
- [Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture](https://scholariq.org/papers/using-design-space-exploration-for-finding-schedules-with-guaranteed-reaction/)
- [MPICH for FC-based Token-Routing Switch-Network](https://scholariq.org/papers/mpich-for-fc-based-token-routing-switch-network/)
- [Enhanced packet routing queuing model in optical burst switching network using queue-based dynamic optical route scheduling](https://scholariq.org/papers/enhanced-packet-routing-queuing-model-in-optical-burst-switching-network-using/)

## Topic primary papers

- [Microarchitecture of a High-Radix Router](https://scholariq.org/papers/microarchitecture-of-a-high-radix-router/)
- [NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?](https://scholariq.org/papers/noc-architectures-for-silicon-interposer-systems-why-pay-for-more-wires-when-you/)
- [1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS](https://scholariq.org/papers/1-1-v-1-ghz-communications-router-with-on-chip-body-bias-in-150-nm-cmos/)
- [Xmesh: A Mesh-Like Topology for Network on Chip](https://scholariq.org/papers/xmesh-a-mesh-like-topology-for-network-on-chip/)
- [MPICH for FC-based Token-Routing Switch-Network](https://scholariq.org/papers/mpich-for-fc-based-token-routing-switch-network/)
- [A High Performance Computing Platform Based on a Fibre-Channel Token-Routing Switch-Network](https://scholariq.org/papers/a-high-performance-computing-platform-based-on-a-fibre-channel-token-routing/)
- [On the communication structures of hyper-ring and hypercube multicomputers](https://scholariq.org/papers/on-the-communication-structures-of-hyper-ring-and-hypercube-multicomputers/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.