# Low-power high-performance VLSI design

**Type:** Topics  
**Canonical URL:** https://scholariq.org/topics/low-power-high-performance-vlsi-design/

## Facts

| Field | Value |
| --- | --- |
| Description | This cluster of papers focuses on the design and optimization of low-power VLSI circuits, with an emphasis on techniques such as approximate computing, subthreshold operation, and leakage reduction. The papers also address challenges related to process variation, statistical timing analysis, and energy efficiency in CMOS technology at the nanometer scale. |
| Domain | Physical Sciences |
| Field | Engineering |
| OpenAlex ID | t10363 |
| Works | 33 |

## Topic papers all

Showing 15 of 33.

- [Chaste: An Open Source C++ Library for Computational Physiology and Biology](https://scholariq.org/papers/chaste-an-open-source-c-library-for-computational-physiology-and-biology/)
- [A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput](https://scholariq.org/papers/a-90-nm-1-8-v-512-mb-diode-switch-pram-with-266-mb-s-read-throughput/)
- [A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets](https://scholariq.org/papers/a-highly-reliable-memory-cell-design-combined-with-layout-level-approach-to/)
- [A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment](https://scholariq.org/papers/a-45-nm-single-port-and-dual-port-sram-family-with-robust-read-write-stabilizing/)
- [Designing Asynchronous Circuits using NULL Convention Logic (NCL)](https://scholariq.org/papers/designing-asynchronous-circuits-using-null-convention-logic-ncl/)
- [Optimization of NULL convention self-timed circuits](https://scholariq.org/papers/optimization-of-null-convention-self-timed-circuits/)
- [A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput](https://scholariq.org/papers/a-90nm-1-8v-512mb-diode-switch-pram-with-266mb-s-read-throughput/)
- [Uncle - An RTL Approach to Asynchronous Design](https://scholariq.org/papers/uncle-an-rtl-approach-to-asynchronous-design/)
- [Delay-insensitive gate-level pipelining](https://scholariq.org/papers/delay-insensitive-gate-level-pipelining/)
- [A low-power 64-point pipeline FFT/IFFT processor for OFDM applications](https://scholariq.org/papers/a-low-power-64-point-pipeline-fft-ifft-processor-for-ofdm-applications/)
- [1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS](https://scholariq.org/papers/1-1-v-1-ghz-communications-router-with-on-chip-body-bias-in-150-nm-cmos/)
- [A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic](https://scholariq.org/papers/a-robust-input-voltage-adaptive-and-low-energy-consumption-level-converter-for/)
- [Designing Asynchronous Circuits using NULL Convention Logic (NCL)](https://scholariq.org/papers/designing-asynchronous-circuits-using-null-convention-logic-ncl-2/)
- [Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction](https://scholariq.org/papers/extending-3-bit-burst-error-correction-codes-with-quadruple-adjacent-error/)
- [Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology](https://scholariq.org/papers/multi-threshold-null-convention-logic-mtncl-an-ultra-low-power-asynchronous/)

## Topic primary papers

- [A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment](https://scholariq.org/papers/a-45-nm-single-port-and-dual-port-sram-family-with-robust-read-write-stabilizing/)
- [Designing Asynchronous Circuits using NULL Convention Logic (NCL)](https://scholariq.org/papers/designing-asynchronous-circuits-using-null-convention-logic-ncl/)
- [Optimization of NULL convention self-timed circuits](https://scholariq.org/papers/optimization-of-null-convention-self-timed-circuits/)
- [Uncle - An RTL Approach to Asynchronous Design](https://scholariq.org/papers/uncle-an-rtl-approach-to-asynchronous-design/)
- [Delay-insensitive gate-level pipelining](https://scholariq.org/papers/delay-insensitive-gate-level-pipelining/)
- [A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic](https://scholariq.org/papers/a-robust-input-voltage-adaptive-and-low-energy-consumption-level-converter-for/)
- [Designing Asynchronous Circuits using NULL Convention Logic (NCL)](https://scholariq.org/papers/designing-asynchronous-circuits-using-null-convention-logic-ncl-2/)
- [Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology](https://scholariq.org/papers/multi-threshold-null-convention-logic-mtncl-an-ultra-low-power-asynchronous/)
- [Novel Approximate Multiplier Designs for Edge Detection Application](https://scholariq.org/papers/novel-approximate-multiplier-designs-for-edge-detection-application/)
- [Error Diluted Approximate Multipliers Using Positive And Negative Compressors](https://scholariq.org/papers/error-diluted-approximate-multipliers-using-positive-and-negative-compressors/)
- [Design and Evaluation of In-Exact Compressor based Approximate Multipliers](https://scholariq.org/papers/design-and-evaluation-of-in-exact-compressor-based-approximate-multipliers/)
- [Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays](https://scholariq.org/papers/timing-yield-driven-clock-skew-scheduling-considering-non-gaussian-distributions/)
- [An Architecture of a True Single Phase Clock D Flip-flop utilizing 45nm Technology](https://scholariq.org/papers/an-architecture-of-a-true-single-phase-clock-d-flip-flop-utilizing-45nm/)
- [DMA SRAM TEGにより解析したSRAMのスタティックノイズマージンにおけるDIBLばらつきの影響(IEDM特集(先端CMOSデバイス・プロセス技術))](https://scholariq.org/papers/dma-sram-teg-sram-dibl-iedm-cmos/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.