# VLSI and Analog Circuit Testing

**Type:** Topics  
**Canonical URL:** https://scholariq.org/topics/vlsi-and-analog-circuit-testing/

## Facts

| Field | Value |
| --- | --- |
| Description | This cluster of papers focuses on various aspects of testing Very Large Scale Integration (VLSI) circuits, including techniques such as test data compression, embedded cores testing, scan testing, analog circuit fault diagnosis, BIST schemes, test access architectures, low-power testing, and delay fault testing. |
| Domain | Physical Sciences |
| Field | Computer Science |
| OpenAlex ID | t11032 |
| Works | 17 |

## Topic papers all

Showing 15 of 17.

- [Algebraic decision diagrams and their applications](https://scholariq.org/papers/algebraic-decision-diagrams-and-their-applications-2/)
- [At-speed delay characterization for IC authentication and Trojan Horse detection](https://scholariq.org/papers/at-speed-delay-characterization-for-ic-authentication-and-trojan-horse-detection/)
- [Application of heuristic search and information theory to sequential fault diagnosis](https://scholariq.org/papers/application-of-heuristic-search-and-information-theory-to-sequential-fault/)
- [Constraint-based watermarking techniques for design IP protection](https://scholariq.org/papers/constraint-based-watermarking-techniques-for-design-ip-protection/)
- [An Analytic-Iterative Redundancy Resolution Scheme for Cable-Driven Redundant Parallel Manipulators](https://scholariq.org/papers/an-analytic-iterative-redundancy-resolution-scheme-for-cable-driven-redundant/)
- [NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?](https://scholariq.org/papers/noc-architectures-for-silicon-interposer-systems-why-pay-for-more-wires-when-you/)
- [Uncle - An RTL Approach to Asynchronous Design](https://scholariq.org/papers/uncle-an-rtl-approach-to-asynchronous-design/)
- [A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS](https://scholariq.org/papers/a-1-0625-sim-14-025-gb-s-multi-media-transceiver-with-full-rate-source-series/)
- [Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems](https://scholariq.org/papers/hardware-resource-virtualization-for-dynamically-partially-reconfigurable/)
- [2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS](https://scholariq.org/papers/2-1-28gb-s-560mw-multi-standard-serdes-with-single-stage-analog-front-end-and-14/)
- [A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS](https://scholariq.org/papers/a-1-0625-to-14-025gb-s-multimedia-transceiver-with-full-rate-source-series/)
- [Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays](https://scholariq.org/papers/timing-yield-driven-clock-skew-scheduling-considering-non-gaussian-distributions/)
- [WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design](https://scholariq.org/papers/wcomp-waveform-comparison-tool-for-mixed-signal-validation-regression-in-memory/)
- [A New FPGA Packing Algorithm Based on the Modeling Method for Logic Block](https://scholariq.org/papers/a-new-fpga-packing-algorithm-based-on-the-modeling-method-for-logic-block/)
- [A high utilization rate routing algorithm for modern FPGA](https://scholariq.org/papers/a-high-utilization-rate-routing-algorithm-for-modern-fpga/)

## Topic primary papers

- [Application of heuristic search and information theory to sequential fault diagnosis](https://scholariq.org/papers/application-of-heuristic-search-and-information-theory-to-sequential-fault/)
- [WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design](https://scholariq.org/papers/wcomp-waveform-comparison-tool-for-mixed-signal-validation-regression-in-memory/)
- [Manufacturing Setup for 4 nm Semiconductor Integrated Circuits in India: Current Scenario and Opportunities](https://scholariq.org/papers/manufacturing-setup-for-4-nm-semiconductor-integrated-circuits-in-india-current/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.