# VLSI and FPGA Design Techniques

**Type:** Topics  
**Canonical URL:** https://scholariq.org/topics/vlsi-and-fpga-design-techniques/

## Facts

| Field | Value |
| --- | --- |
| Description | This cluster of papers focuses on the design, optimization, and challenges of field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). It covers topics such as FPGA architecture, analog circuit design, graph partitioning for parallel computing, power optimization, CMOS design, and dynamic load balancing in computational mechanics. |
| Domain | Physical Sciences |
| Field | Engineering |
| OpenAlex ID | t11522 |
| Works | 10 |

## Topic papers all

- [Large‐scale topology optimization using preconditioned Krylov subspace methods with recycling](https://scholariq.org/papers/large-scale-topology-optimization-using-preconditioned-krylov-subspace-methods/)
- [Designing Asynchronous Circuits using NULL Convention Logic (NCL)](https://scholariq.org/papers/designing-asynchronous-circuits-using-null-convention-logic-ncl/)
- [Optimization of NULL convention self-timed circuits](https://scholariq.org/papers/optimization-of-null-convention-self-timed-circuits/)
- [Delay-insensitive gate-level pipelining](https://scholariq.org/papers/delay-insensitive-gate-level-pipelining/)
- [SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators](https://scholariq.org/papers/somalib-library-of-exact-and-approximate-activation-functions-for-hardware/)
- [Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays](https://scholariq.org/papers/timing-yield-driven-clock-skew-scheduling-considering-non-gaussian-distributions/)
- [WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design](https://scholariq.org/papers/wcomp-waveform-comparison-tool-for-mixed-signal-validation-regression-in-memory/)
- [A New FPGA Packing Algorithm Based on the Modeling Method for Logic Block](https://scholariq.org/papers/a-new-fpga-packing-algorithm-based-on-the-modeling-method-for-logic-block/)
- [An efficient multi-way algorithm for balanced partitioning of VLSI circuits](https://scholariq.org/papers/an-efficient-multi-way-algorithm-for-balanced-partitioning-of-vlsi-circuits/)
- [A high utilization rate routing algorithm for modern FPGA](https://scholariq.org/papers/a-high-utilization-rate-routing-algorithm-for-modern-fpga/)

## Topic primary papers

- [A New FPGA Packing Algorithm Based on the Modeling Method for Logic Block](https://scholariq.org/papers/a-new-fpga-packing-algorithm-based-on-the-modeling-method-for-logic-block/)
- [An efficient multi-way algorithm for balanced partitioning of VLSI circuits](https://scholariq.org/papers/an-efficient-multi-way-algorithm-for-balanced-partitioning-of-vlsi-circuits/)
- [A high utilization rate routing algorithm for modern FPGA](https://scholariq.org/papers/a-high-utilization-rate-routing-algorithm-for-modern-fpga/)

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Source: ScholarIQ — public research metadata, principally OpenAlex. See https://scholariq.org/sources/ for provenance and https://scholariq.org/methodology/ for what these figures mean.