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Advancements in PLL and VCO Technologies
TopicLeading institutions, researchers & key papers
This cluster of papers focuses on the design, analysis, and optimization of phase-locked loops (PLLs) and related components in high-speed circuits. Topics include frequency synthesizers, time-to-digital converters, jitter analysis, digital PLLs, charge pumps, clock recovery techniques, delta-sigma modulators, and their application in high-speed communication systems.
19
Works
IDs:OpenAlex
How has Advancements in PLL and VCO Technologies's publication output changed over time?
ScholarIQpublication output · 2006–2025
Output grew0% over the shown period — from 1 works in 2006 to 1 in 2025.
1
1
2
2
2
1
200620092010201120142025
What are the most-cited papers on Advancements in PLL and VCO Technologies?
ScholarIQmost cited works
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
Hiroshi Kimura, Pervez Aziz, Tai Jing, Ashutosh Kumar Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael Cai Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong
S83637746. 201496 CitationsOPEN ACCESS
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, M. Fukaishi
S83637746. 201088 Citations
A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS
Freeman Zhong, Shaolei Quan, Wing Liu, Pervez Aziz, Tai Jing, Jen Dong, C. Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Xiaoyue Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chai Palusa, Anil Rajashekara, Ashutosh Kumar Sinha, Charlie Zhong, Eric Zhang
S83637746. 201154 Citations
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber
Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, A. Vasani, Anubhav Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Balaji Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz
200942 Citations
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-<tex>$muhbox m$</tex>SiGe BiCMOS Technology
Anubhav Garg, Anthony Chan Carusone, Sorin P. Voinigescu
S83637746. 200633 Citations
Where is Advancements in PLL and VCO Technologies research published, and who funds it?
ScholarIQvenues & funding sources
TOP JOURNALS
S83637746271
TOP FUNDERS
National Science Foundation—
NIH—
Wellcome Trust—
European Research Council—
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How much of the research on Advancements in PLL and VCO Technologies is open access?
ScholarIQopen access share
11%OPEN ACCESS
Gold
0%
Green
0%
Hybrid
0%
Bronze
11%
Closed
89%
Related on ScholarIQ
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
Paper
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter
Paper
A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS
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A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio
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21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber
Paper
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-<tex>$muhbox m$</tex>SiGe BiCMOS Technology
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